Fbb Cmos Tapered Buffer With Optimal Vth Selection
This paper represents fixed body biased CMOS Tapered Buffer which is designed to minimize the PDP (Power Delay Product) of the circuit. CMOS Tapered Buffers are often used for driving large capacitive load at high speed. Since there are tradeoffs between performance parameters of Buffer for minimizing its PDP value and due to technology constraints on the threshold voltage of MOS; one can vary the Vth up to certain limit while keeping the VDD constant. The proposed work is helpful in designing power efficient CMOS Tapered Buffer. This is found that in proposed Buffer when Vth value for the first stage of inverter is taken between the range of (0.2VDD - 0.4 VDD), its performance gets improved in terms of power dissipation. This analysis is verified by simulating the 2-stage Tapered buffer using standard 180nm CMOS technology in Cadence environment. Analysis performed on the schematic shows that FBB (Fixed Body Bias) Tapered Buffer reduces the average power dissipation across capacitive load by 77% and static power has been reduced to 18.3% at very less penalty in delay. Hence the proposed approach is suitable in the design of low power buffer for increasing the current capability of logic gate at optimal speed.
 Ashok Srivastava and Chuang Zhang, “An Adaptive Body-Bias Generator for Low Voltage CMOS VLSI Circuits”, ISSN: 1550-1329 print / 1550-1477 International Journal of Distributed Sensor Networks, 4: 213–222, 2008. http://dx.doi.org/10.1080/15501320802001259
 Brian .S Cherkauer, Student Member IEEE, “A Unified Methodology for CMOS Tapered Buffer” IEEE Transactions on VLSI Systems, Volume 3– No.1, 1995. http://dx.doi.org/10.1109/92.365457
 Dinesh Sharma and Rajesh Mehra, “Low Power, Delay Optimized Buffer Design using 70nm CMOS Technology,” International Journal of Computer Applications (0975 – 8887), Volume 22, No.3, May 2011. http://dx.doi.org/10.5120/2565-3526
 H. C. Lin and L. W. Linholm, “An optimized output stage for MOS integrated circuits,” IEEE J. Solid-State Circuits, vol. SC-10, no. 2, pp. 106–109, Apr. 1975. http://dx.doi.org/10.1109/JSSC.1975.1050569
 H. J. M. Veendrick, “Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits,” IEEE J. Solid-State Circuits, vol. SC-19, no. 4, pp.468-473, Aug. 1984. http://dx.doi.org/10.1109/JSSC.1984.1052168
 K. A. Bowman, B. L. Austin, and J. C. Eble, “A physical alpha-power law MOSFET Model,” in Proc. Int. Symp. Low Power Electron Design (ISLPED’99), pp. 99–119, 1999.
 Kang, Sung-Mo and Leblebici Y., ”CMOS Digital Integrated Circuits”, McGraw Hill Pub, 2003.
 Liming Xiu “VLSI Circuit Design Methodology Demystified (A Conceptual Taxonomy)”, IEEE Press, Wiley-Interscience A John Wiley & Sons, Inc., Publication, 2008.
 M. Pedram, “Design technologies for Low Power VLSI”, In Encyclopedia of Computer Science and Technology, Vo. 36, Marcel Dekker, Inc., 1997, pp. 73-96.
 N. C. Li, G. L. Haviland and A. A. Tuszynski, “CMOS tapered buffer,” IEEE I.S.SC., vol. 1005-1008, 1990. http://dx.doi.org/10.1109/4.58293
 Panda, P.R; Silpa, B.V.N.; Shrivastava, A; Gummidipudi, K., “Power-efficient System Design” 2010, X, 253p, Hardcover, ISBN: 978-1-4419-6387-1
 Pandit Nad, Dhananjaya A and Ms.Suma M S “Optimization of Delay and Leakage using Body Bias” International Journal of Engineering Research & Technology (IJERT) ISSN: 2278- 0181 www.ijert.org Vol. 2 Issue 6, June – 2013.
 R.C. Jaeger, “Comments on ‘An optimized output stage for integrated circuits’,” IEEE J. Solid-State Circuits, vol. SC-10, no. 3, pp. 185–186, June. 1975. http://dx.doi.org/10.1109/JSSC.1975.1050587
 Rinze Ida Mechtildis Peter Meijer,” Body Bias Aware Digital Design” Eindhoven: Technische Universiteit Eindhoven, 2011. ISBN: 978-90-386-2920-9 NUR: 959
 Sutherland, B. Sproull, D. Harris, “Logical Effort: Design Fast CMOS Circuits”, Morgan Kaufmann Publishers, 1999 January.
 T. Chen and S. Naffziger, “Comparison of Adaptive Body Bias (ABB) and Adaptive Supply Voltage (ASV) for Improving Delay and Leakage Under the Presence of Process Variation,” IEEE Transactions on VLSI Systems, Vol.11, No.5, pp. 888-899, October 2003. http://dx.doi.org/10.1109/TVLSI.2003.817120
 T. Sakurai, A. R. Newton, “Alpha-power law MOSFET model and its applications to CMOS inverter and other formulas” IEEE J.Solid-State Circuits, vol. 25, pp.584-594, April 1990.http://dx.doi.org/10.1109/4.52187
 Tadahiro Kuroda “Optimization and control of VDD and VTH for low-power, high-speed CMOS design“in Proceedings of IEEE/ACM international conference on Computer-aided design San Jose, California, Page(s): 28 -34, 2002. http://dx.doi.org/10.1109/ICCAD.2002.1167510
Copyright (c) 2014 Journal on Today's Ideas - Tomorrow's Technologies
This work is licensed under a Creative Commons Attribution 4.0 International License.
Articles in Journal on Today's Ideas - Tomorrow's Technologies (J. Today’s Ideas - Tomorrow’s Technol.) by Chitkara University Publications are Open Access articles that are published with licensed under a Creative Commons Attribution- CC-BY 4.0 International License. Based on a work at https://jotitt.chitkara.edu.in. This license permits one to use, remix, tweak and reproduction in any medium, even commercially provided one give credit for the original creation.
View Legal Code of the above mentioned license, https://creativecommons.org/licenses/by/4.0/legalcode
View Licence Deed here https://creativecommons.org/licenses/by/4.0/
|Journal on Today's Ideas - Tomorrow's Technologies by Chitkara University Publications is licensed under a Creative Commons Attribution 4.0 International License.
Based on a work at https://jotitt.chitkara.edu.in